The present invention relates to a method and a corresponding circuit for providing active impedance compensation. More particularly, the present invention relates to a system and method by which a circuit connecting a slave device to a high speed bus incorporates means for actively providing impedance compensation.
A contemporary bus system is conceptually illustrated in FIG. 1. Within this system a master 10 having an interface 14 is connected to a channel 12 which terminates in one or more termination resistors 13. One or more slave devices 11 are also connected to channel 12 between master 10 and termination resistor(s) 13. Channel 12 comprises a plurality of signal lines communicating data and control information between master 10 and the slave devices 11.
The exemplary bus system shown in FIG. 1 is implemented on a printed circuit board (PCB). That is, master 10 and slave devices 11 are mounted on the PCB, and the signal lines forming channel 12 are implemented, at least in part, by metal traces formed on the PCB.
Ideally this bus system is implemented with carefully balanced (or matched) impedances. By matching the impedance of master interface 14 and termination resistor(s) 13, as well as the effective impedance of the signal lines forming channel 12, signals transmitted between master 10 and slave devices 11 do not result in unwanted signal reflections which reduce the signal to noise ratio on the channel.
The signal lines forming channel 12 may be described according to the model shown in FIG. 2A, where the electrical characteristics of each signal line are expressed as an inductance component LPCB and a capacitive component CPCB. From this model, signal line impedance (Z) may be expressed as:Z=(LPCB/CPCB)1/2  (1)where LPCB and CPCB are the per unit length inductance and capacitance of the PCB trace.
When there are devices connected to the PCB trace with regular spacing, the impedance changes due to device loading. The loading effects of each slave device connection to a signal line may be described in relation to the model shown in FIG. 2B. Here, the loading effects are represented by the series combination of Li, Ci, and Ri placed in parallel with CPCB. For the signal frequencies presently contemplated, the loading effects of Ci predominate over Li and Ri. Accordingly, the electrical behavior of the loaded signal line may be understood from the model shown in FIG. 2C. Channel impedance (Zch) may be expressed as:Zc˜{LPCB/[CPCB+(Ci÷pitch)]}1/2  (2)where pitch is the length of the signal lines between slave devices and Ci is the total input capacitance of a slave device.
In view of the foregoing, system designers may vary the impedance of the signal line traces on the PCB and the device pitch in order to define a nominal channel having a specific target impedance. The term “target” is used because in reality some amount of variation around the nominal impedance occurs due to process variations in the manufacture of the PCB and the various bus system components. Currently, such impedance variations may be controlled to within +/−10% of the target impedance.
As is well understood by those of ordinary skill in the art, a signal traversing a transmission line having impedance variations or discontinuities will generate unwanted signal reflections. This phenomenon is further illustrated in FIG. 3.
FIG. 3 conceptually illustrates the transmission line of the channel between master 10 and termination resistor(s) 13. Channel 12 (shown in dashed line) comprises a number of PCB portions, i.e., those portions of the channel formed by signal line traces on or through PCB 20 having a first impedance Z1, and a number of module portions, i.e., those portions of the channel formed by signal lines integral to connected daughterboard modules having a second impedance Z2. Despite design attempts to match Z1 and Z2, variations in PCB manufacturing processes typically result in impedance discontinuities between the channel portions characterized by Z1 and Z2.
When a signal traverses these impedance discontinuities a number of discrete signal reflections Sf1 . . . Sfn result, as shown in relation to the model transmission line 30 of FIG. 3. The effect of these unwanted signal reflections is illustrated in FIGS. 4A through 4D. The single pulse signal shown in FIG. 4A when introduced into the bus system of FIG. 3 may produce the signal shown in 4B when influenced by the unwanted signal reflections. Similarly, the input signal shown in FIG. 4C might produce the signal shown FIG. 4D.
Such resulting signals may occur, for example, when the multiple impedance discontinuities shown in FIG. 3 occur at spacings which correspond to odd multiples of the input signal's quarter wavelength. In such a circumstance, the unwanted reflections tend to add up constructively. Such constructive interference of multiple reflections leads to large timing and voltage errors on the channel. Analogously, destructive interference of multiple reflections can reduce signal margins and lead to a loss of signal coherency.